This invention relates to differential signaling drivers, and more particularly pseudo-emitter-coupled logic (PECL) drivers.
Low-power circuits have employed full-voltage-swing signaling. For example, a complementary metal-oxide-semiconductor (CMOS) output can swing from ground to the power-supply voltage, such as 0-5 or 0-3 volts. However, as signal speeds increase, unwanted electromagnetic interference (EMI) is increasingly generated, and signal quality deteriorates due to reflections, ringing, and voltage undershoot.
Reducing the voltage swing reduces these undesirable effects. However, noise margin is also reduced as the voltage swing is cut. Noise margin can be improved by using two signal wires to transmit a logical signal, rather than just one wire. Such differential signaling has been used for many years in bipolar emitter-coupled logic (ECL) systems.
More recently, the benefits of differential ECL signaling and low-power CMOS have been combined in what is known as pseudo-emitter-coupled logic (PECL). PECL uses differential signaling and current-steering through CMOS transistors. Data rates as high as 1 Giga-bit per second are desired.
FIG. 1A shows a differential signaling scheme. Driver 10 drives lines Y1, Y2 with opposite data. Current is steered among lines Y1, Y2 so that the amount of current passing through each of resistors 14 varies with the data. The I*R voltage drop across resistors 14 can be sensed by receiver 12. The other terminal of resistors 14 is connected to terminating voltage VTT.
FIG. 1B highlights the small voltage swing of differential signaling. Lines Y1, Y2 are driven to opposite states, depending on the data transmitted. The logic high level is reached when Y1 is driven to a VOH voltage, while the complement line Y2 is driven to a VOL level. For the logic low level, Y1 is driven to the VOL voltage, while the complement line Y2 is driven high to a VOH level.
To minimize EMI radiation and signal distortion, VOH and VOL are chosen to be close to each other. This minimizes the voltage swing from VOL to VOH. For example, VOL can be set to 1.66 volts, while VOH is set to 2.33 volts in systems with 3-volt supplies. The signal swing is thus reduced to about 700 mV. The terminating voltage VTT can be set to 2 volts below Vcc, or about 1.3 volts. This is below both VOH and VOL.
When 50-ohm terminating resistors are used for lines Y1, Y2, the amount of current to produce the desired VOH and VOL levels can be calculated using Ohm""s law. The current switched is I=V/R=0.33v/50=6.6 mA.
FIG. 2 shows a prior-art differential amplifier for driving a pair of differential outputs. Bias circuit 20 generates bias voltages for current sources 22, 24 and current sink 26 that produce the target current values I1 and I2. Data control circuit 30 receives the data input DIN and generates true and complement data signals. The complement data is applied to the gate of differential transistor 28, while the true data is applied to the gate of differential transistor 29.
When the data is high, the gate of differential transistor 29 is at a high voltage, causing it to conduct current I1 from current source 24 to current sink 26. This causes output Y2 to fall in voltage to VOL. Since the complement data is low, the gate of differential transistor 28 is low, reducing the current through differential transistor 28. The effective resistance of differential transistor 28 rises, causing line Y1 to rise in voltage. The I1 current from current source 22 is diverted to charging line Y1. Thus Y1 rises in voltage to VOH while Y2 falls in voltage to VOL.
When differential transistor 28 completely turns off, VOH is I1*50 ohm above VTT. Current I1 can then be designed to meet a desired VOH. Voltage VOL is (I2xe2x88x92I1)*50 ohm above VTT, which is the excess sinking current from current sink 26 that discharges line Y2 through the 50-ohm terminating resistor.
While such a differential driver is useful, large currents I1, I2 are needed to quickly charge and discharge the Y1, Y2 lines when high speeds are necessary. However, these currents may also be limited by VOH, VOL requirements, limiting the switching speed.
Another problem is that a large standby current is required by the differential driver. Current sources 22, 24 and current sink 26 remain on after the data has switched to maintain VOH and VOL levels on lines Y1, Y2. The large currents needed for high-speed switching causes a large power drain even when no switching occurs. This is undesirable for low-power applications.
What is desired is a differential driver for low-power applications. A PECL driver with low-voltage swing is desirable. A high-switching speed differential driver with low standby power is desired.